automated tests - Get current timestamp VHDL -

To create random seeds, I would like to get system timestamps in my VHDL test bench.

How can I do this?

By the way, I am using RandomPkg

presenting.

For a general VHDL approach, you can pass the system bench unit as normal . If the test looks like a bench:

  the unit is BD_TB normal (seed: natural: = 0); End unit; Sim's FALSE report of Seed's architecture "Seed =" and "Integer'image (Seed) Seriousness Note; End Architecture;   
 Then Command to run, compile and run on Linux with Model Sim Simulator The line can be:  
 > Vliv function & gt; Vcom seed_tb.hd> sec  date +% s  seconds since 71 71-01 Give vsim cd_tb-c-gsED = 'date;% s` -do "run; Exit   
 01, which will fit in the VHDL natural type (even for another 25 years).  
 The advantage of the approach is Simulation with the same seed from the command line is easier to run again. Case debugging is necessary.