system verilog - How to bind an interface to multiple ports without duplicating code? -

In this example, how do I create a single interface bind statement, which can be reused for both ports of the module Is:

  module adderSubtractor2 (input clk, input [7: 0] a0, input [7: 0] b0, input doAdd0, // if it is 1, add; reduce other output reg [8: 0] Result 0 ifdef has_UNIT_2, input [7: 0] A1, input [7: 0] b1, input doAdd1, // if it is 1, add and reduce output reg [8: 0] result1 `Endif); // ... endmodule interfaces adder subtractor_if (input bit clk, input [7: 0] a, input [7: 0] b, input doAdd, input [8: 0] result); // ... endinterface: adderSubtractor_if // BIND statement (s) here // test that will be run on the DUT program automatic test (adder subtractor_if addSub); Beginners start / interface endprogram // test / do stuff with top level testbench module TestBench; Reg clk; Copper subcontact 2 dat (.ccl (clk)); Test0 test (dt.reader subtractor_if0); `Ifdef HAS_UNIT_2 test1 (dut.adderSubtractor_if1); `Endeiff // ... and MDI / TestBench    
 
 
 I believe that What you are doing, again looking for the parametric interface.  
 In general, masking ports with `ifdef is very risky, and you will have very good reason to do this. This topic has already been discussed.  
 I do not see any reason to use ifdef in your case. You can:  
 
 Define parameter NUM_OF_INSTANCES  
 
 Define all (except clique and RST) ports of your module as pack arrays. I.e.  
 input [1: NUM_OF_INSTANCES] [7: 0] a;   
 
 Use the "multiple generator" inside the module P>  
 Use the parametrizable interface and tie it to the ports of the modem in general.   
 Hope it helps.