hdl - Are there any advantages to having fewer levels of wrappers in verilog? -

Specifically, I'm asking that there are some advantages of lower level in hierarchical design.

Thank you!

Thank you!

OK, so it depends on how you have installed your barriers and what tool do you use Are there. So if you allow the device to "level" your design on compilation / synthesis / PNR (location and route) (make sure that xilinx's vivado and ise also makes it and rhythm) between a flat design and a There should be no difference in performance Hierarchical design The reason for this is that the tool basically ignores the limitations of files, when adding logic and places and not so.

If you prepare a pure list on the other side or even the tool keeps them out and try again and share them individually, you remember the shared logic Or can be trapped with at least optimal location or routing status.

Overall, if you are interested in displaying your design, do as much of equipment as you can, the more freedom you do, the more work you do. Therefore, if you use wrappers (a good idea for human readability), make sure that the device is given freedom by using the flatten option.