warnings - How to ignore specific unused wires in Verilog? -

There are some strings and ports in my design that are deliberately unused, but what I want to keep.
How do I tell my Xilinx Verilog Synthesizer to avoid giving "unused" warnings about those specific stars?

Apparently VHDL has a open keyword for it, but I do not know what its equivalent is in Verilog.

Connect them to dummy strings and (* keep = "soft" *) for those stars (names do not matter in the name).

Example

  (* Keep = "soft" *) Wire [7: 0] unconnected_received_data; Uart_receive uart_receive (.STST), CLK (CLK), RXD (UTHRXD), DATA (unrelated). RXDIADI (RxD_RDD);   
  This example will not generate any warning.   (* Keep = "soft" *) on   
 
 :  
 
 As a result, net synthesis is preserved during , But to implement it all the freedom is given to the implementation tool. Conceptually, you are specifying a KEEP = TRUE for synthesis only, but a KEEP = FALSE for the implementation tool.